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ZBQ4GA08A 4Gb DDR4 SDRAM

The transfer rates of 4Gb DDR4 can be up to 3200Mbps for general applications which requires large memory
density and high bandwidth. The chip is designed to comply with the following key DDR4 SDRAM feature such
as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination supported and
Asynchronous Reset. All of the control and address inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion.
The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style

⚫VDD = VDDQ = 1.2V +/- 0.06V
⚫VPP = 2.5V (2.375V~2.75V)
⚫4Gb DDR4 SDRAM x8 = 16 Banks (4 bank group) / 4Gb DDR4 SDRAM x16 = 8 Banks (2 bank group)
⚫8-bit pre-fetch
⚫Burst length of 8 and burst chop of 4
⚫Bi-directional / Differential Data-Strobe
⚫On Die Termination supported
⚫Asynchronous Reset
⚫ZQ calibration supported
⚫Programmable CAS Latency (posted CAS): 10,11,12,13,14,15,16,17,18,19,20,21,22
⚫Programmable Additive Latency: 0, CL-2 or CL-1 clock
⚫ Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600); 10,12 (DDR4-1866); 11,14 (DDR4-2133);
12,16 (DDR4-2400); 14,18 (DDR4-2666); 16, 20 (DDR4-2933 and DDR4-3200)
⚫Average Refresh Cycle (Tcase of 0℃~ 95 ℃)
-7.8 μs at 0℃ ~ 85℃
-3.9 μs at 85℃ ~ 95℃
⚫JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
⚫DLL off mode is supported
⚫CA parity (Command Address Parity) mode is supported
⚫Data Bus write CRC (Cyclic Redundancy Check) is supported
⚫POD (Pseudo Open Drain) interface for data input/output
⚫Internal VREF for data inputs
⚫External VPP for DRAM Activating Power
⚫PPR (Post Package Repair) mode is supported
⚫Low Power Self Refresh mode is supported
⚫All of products are compliance with the RoHS directive