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ZD35Q2GC-IB 2Gb
ZD35X2GAXXX is a 256Mx8bit with spare 8Mx8 bit capacity.
The device is offered in 3/1.8 Vcc Power Supply, and with SPI interface.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid
data while old data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series
connected Flash cells. Program operation allows the 2112-byte page writing in typical 300us and an
erase operation can be performed in typical 2 ms on a 128K-byte block.
Data in the page can be read out at 10ns cycle time per word (3V version), and at 12ns cycle time per
word (1.8V version). The on-chip Program/Erase Controller automates all program and erase functions
including pulse repetition, where required, and internal verification and margining of data.
An internal 4-bit ECC logic is implemented in the chip, which is enabled by default. The internal ECC can
be disabled or enabled again by command. W
■ Serial Peripheral Interface
－ Mode 0 and Mode 3
■ Standard, Dual, Quad SPI
－Standard SPI: SCLK, CS#, SI, SO
－Dual SPI: SCLK, CS#, SIO0, SIO1
－Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
■ SUPPLY VOLTAGE
－VCC = 1.8/3.0 Volt co
re supply voltage for
Program, Erase and Read operations
PAGE READ / PROGRAM
－(2048+64 spare) byte
－Random access: 25us (w/o ECC), 90us(w/ ECC)
－Serial access:
104MHz (1.8V/3.3V)
－Page program time: 300us (Typ)
■ FAST BLOCK ERASE
－ Block size: (128K + 4K) bytes
－Block erase time: 2ms (Typ)
■ MEMORY CELL ARRAY
－ (2K + 64) bytes x 64 pages x 2048 blocks
■ ELECTRONIC SIGNATURE
－ Manufacturer Code
－ Device Code
■ STATUS REGISTER
■ HARDWARE DATA PROTECTION
－ Enable/Disable protection with WP# Pin
－ Top or Bottom, Block selection combination
■ DATA RETENTION
－Cycling: 100K Program / Erase cycles
－Data retention: 10 Years (4bit/512byte ECC)
－Internal ECC can be enabled (4bit ECC)
－ Block zero is a valid block and will be valid for at
least 1K program-erase cycles with ECC
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