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存储芯片

ZDV4256M16A-14IPH 4Gb,DDR3

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM. It is internally configured as
an octal-bank DRAM.
The 4Gb chip is organized as 32Mbit x16 I/O x 8 banks. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and CK
____
falling). All I/Os are synchronized with a single ended DQS or
differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in
BGA packages.

4GBIT DDR3 DRAM

VDD=VDDQ=1.5V(1.425V~1.575V)

VDD=VDDQ=1.35V(1.28V~1.45V)，backward

compatible to 1.5V applications.

 8 banks

 8n-bit prefetch architecture

 Fully differential clock inputs (CK,CK) operation

 Bi-directional differential data strobe (DQS,DQS )

 On chip DLL align DQ, DQS and DQS

transition

With CK transition

 DM masks write data-in at the both rising and