e•MMC v5.1 compatible. Detail description is referenced by JEDEC Standard
- (Backward compatible to e•MMC v4.5 to v5.0)
Bus mode
- Data bus width: 1bit(default), 4bit and 8bit
- Data transfer rate: up to 400MB/s (HS400) @ 200MHz DDR with 8bit bus width
- MMC I/F Clock Frequency: 0~200MHz
- MMC I/F Boot Frequency: 0~52MHz
Operating Voltage Range
- VCC (NAND/Core): 2.7V ~ 3.6V
- VCCQ (CTRL/IO): 1.7V ~ 1.95V / 2.7V ~ 3.6V
Temperature
- Commerical ( -25℃ ~ 85℃ )
Supports Features
- HS400, HS200, DDR52, SDR52
- High Priority Interrupt (HPI)
- Background Operation, BKOPS Control
- Packed CMD, Command Queuing
- Cache, Cache Flushing Report, Cache Barrier (Optional)
- Partitioning, Partition types, RPMB, RPMB Throughput Improve
- Discard, Trim, Erase, Sanitize
- Write Protect, Secure Write Protection (Optional)
- Lock/Unlock
- Power Off Notification(PON), Sleep/Awake
- Enhance Reliable Write
- Boot feature, Boot partition
- Context IDs, Data Tag, Real Time Clock
- HW/SW Reset
- Configurable driver strength
- Field Firmware Update
- Secure Removal Type (Optional)
- Device Health Report (Optional)
- Production State Awareness (Optional)
- Data Strobe pin, Enhanced Strobe (Optional)
(Bold features are added in eMMC5.1)
